The present invention relates to a voltage tolerant circuit device or method. More specifically, the present invention relates to a 5V tolerant IO scheme using low voltage devices adapted to adjust bias conditions.
In modern CMOS ASIC design, the core circuitry generally operates at a lower voltage than the IO circuits. This provides a core circuitry design that operates at higher speeds with lower power consumption than previous circuitry designs. However, since the maximum operating voltage of such current CMOS ASIC core circuitry designs is also lower, these devices may not be used directly with currently known IO circuits without special design considerations.
This limitation may be further complicated when the maximum device voltage is significantly less than the voltage required for 5V tolerance. Smaller device geometries result in higher device efficiencies, but at the same time lower the maximum device voltage. A design method is contemplated that enables IO devices to utilize more efficient transistors without violating the transistor maximum voltage, enabling other circuitry to benefit from the increased transistor efficiencies.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.